1. Field of the Invention
The present invention relates generally to analog-to-digital converter (ADC) circuits and, more particularly, to successive approximation register (SAR) ADC circuits.
2. Description of Related Art
Successive approximation register (SAR) analog-to-digital converters (ADCs) are popular due to their reasonably fast conversion time, yet moderate circuit complexity. Types of SAR ADCs include resistor string SAR ADCs, capacitor array SAR ADCs, and resistor-capacitor (R-C) hybrid SAR ADCs. R-C hybrid SAR ADCs are often used to reduce non-linearities due to lengthy resistor strings or bulky capacitor arrays in physical layouts.
FIG. 1 is a diagram of one embodiment of a known 10-bit resistor-capacitor (R-C) hybrid SAR ADC 10. The R-C hybrid SAR ADC 10 receives a single-ended analog input voltage “Vin,” and includes a resistor string 12 for generating internal reference voltages. As indicated in FIG. 1, the reference voltages include 16 coarse reference voltages “Vc[15:0]” and 17 fine reference voltages “Vf[16:0].”
Operation of the R-C hybrid SAR ADC 10 may be described as including two phases: an initial sampling phase and a bit cycling phase. During the initial sampling phase, a switch S0 is closed, coupling an output terminal of a comparator 16 to a negative (−) input terminal of the comparator 16 and to a node “N,” wherein a voltage “Vsum” exists between the node N and a ground reference potential (i.e., ground). A switch S1 is set to couple the analog input voltage Vin to one terminal of a largest of 4 binary-weighted capacitors of a capacitor array 14. Switches S2, S3, and S4 are set to couple terminals of the other 3 capacitors to ground.
Opposite terminals of all 4 capacitors of the capacitor array 14 are coupled to the node N. A positive (+) input terminal of the comparator 16 is connected to a reference voltage “Vcm.” It is noted that Vcm=Vrh/2=Vc[8]. (See FIG. 2.)
The comparator 16 drives the node N until the voltage Vsum at the node N is equal to Vcm. The switch S0 is then opened, completing the initial sampling phase. Ideally, at the end of the initial sampling phase, an initial charge Q0, corresponding to the analog input voltage Vin, exists on the node N, wherein Q0=(Vcm−Vin)·8C+Vcm (4C+1C+1C).
During the bit cycling phase, a successive approximation register (SAR) block 18 of the R-C hybrid SAR ADC 10 produces a 10-bit output signal [b9:b0] during 10 consecutive cycles of a “CLOCK” signal. In the embodiment of FIG. 1, the bit decisions made during the bit cycling phase are based on a bit grouping {4, 4, 1, 1}. That is, bits in a first 4-bit group [b9:b6] are determined first during the first 4 cycles of the CLOCK signal. Bits in a second 4-bit group [b5:b2] are then determined during the next 4 cycles of the CLOCK signal, followed by a third 1-bit group [b1] during the ninth cycle of the CLOCK signal, and finally a fourth 1-bit group [b0] during the tenth cycle of the CLOCK signal.
During the bit cycling phase, the switch S1 is set to couple the corresponding terminal of the largest of the 4 binary-weighted capacitors of the capacitor array 14 to a signal line DA1, and the switches S2, S3, and S4 are set to couple the corresponding terminals of the other 3 capacitors to respective signal lines DA2, DA3, and DA4.
FIG. 2 is a diagram of a known embodiment of the resistor string 12 of FIG. 1. As indicated in FIG. 2, the resistor string 12 produces the 16 coarse reference voltages Vc[15:0] and the 17 fine reference voltages Vf[16:0].
Referring back to FIG. 1, during the determination of the bits of the first 4-bit group [b9:b6], a decoder and multiplexers (MUXs) component 20 of the R-C hybrid SAR ADC 10 selectively couples the signal line DA1 to one of the 16 coarse reference voltages Vc[15:0], starting with Vc[8]. The resulting binary search algorithm typically requires 4 cycles of the CLOCK signal to determine the values of the bits of the first 4-bit group [b9:b6]. While the decoder and MUXs component 20 selectively couples the signal line DA1 to one of the 16 coarse reference voltages Vc[15:0], the decoder and MUXs component 20 couples the signal lines DA2, DA3 and DA4 to ground. The voltage Vsum at node N is given by: Vsum=Vcm−Vin·(8C/Ct)+DA1·(8C/Ct)+DA2·(4C/Ct)+DA3·(C/Ct)+DA4·(C/Ct), where Ct=8C+4C+1C+1C=14C. The comparator output signal “CmpOut” is allowed to settle, then latched into the SAR block 18. The SAR block 18 uses the latched value of the CmpOut signal in a binary search algorithm for selecting a reference voltage used during the next step.
Four cycles of the CLOCK signal are required to select a final reference voltage Vc[x] for coupling to the DA1 signal line, where 0≦x≦15. When DA1=Vc[x], the CmpOut signal is asserted (e.g., a logic ‘1’), and when DA1=Vc[x+1], the CmpOut signal is deasserted (e.g., a logic ‘0’). Since each of the 16 reference voltages Vc[15:0] correspond to a 4-bit binary code, the selection of the final reference voltage Vc[x] for the DA1 signal line corresponds to the determination of the bits of the first 4-bit group [b9:b6].
After the bits of the first 4-bit group [b9:b6] are determined, the bits of the second 4-bit group [b5:b2] are determined in a similar fashion. Values of the CmpOut output signal produced by the comparator 16 are used to selectively couple one of 16 fine reference voltages Vf[15:0] to the DA2 signal line. After the CmpOut output signal of the comparator 16 settles, the CmpOut signal is latched into the SAR BLOCK 18, and used to select the next reference voltage. After another 4 cycles of the CLOCK signal, the bits of the second 4-bit group [b5:b2] are determined.
After the bits of the second 4-bit group [b5:b2] are determined, the bit of the third 1-bit group [b1] is determined. During the ninth cycle of the CLOCK signal, a reference voltage selected from the set {Vf[2], Vf[0]} is coupled to the DA3 signal line. After the bit of the third 1-bit group [b1] is determined, the bit of the fourth 1-bit group [b0] is determined. During the tenth cycle of the CLOCK signal, a reference voltage selected from the set {Vf[1], Vf[0]} is coupled to the DA4 signal line. At the end of bit cycling phase, the SAR BLOCK 18 of the R-C hybrid SAR ADC 10 produces the 10-bit output signal [b9:b0].
Single-ended (unbalanced) signals are referenced to a voltage level commonly called a “signal ground.” While the signal ground is typically a negative power supply voltage level, the signal ground may also be a positive voltage supply level or an external reference voltage level. Single-ended signals are typically conveyed via a pair of conductors. A first of the two conductors carries the signal, and the second conductor functions as voltage reference level and/or a current return path. The second conductor is typically connected to the signal ground.
Differential signals are also propagated via a pair of conductors. In this case, however, the conductors carry equal and opposite signals, and the differential signal is a voltage between the conductors. As each signal is equal and opposite, no separate current return path is required. Conductors used to convey a differential signal typically have a constant distance between them, are typically routed together from a source to a destination, and each conductor typically has the same electrical impedance.
Due to their electrical impedances, noise voltages are commonly induced in conductors carrying voltage signals. Examples of noise sources include radiated electromagnetic interference (EMI) and signals on nearby signal lines. “Common-mode noise” is defined as the component of noise voltage that appears equally and in phase on conductors relative to a common reference.
As electrical impedances of conductors carrying single-ended signals are not equal, noise voltages induced in the conductors are not equal. With a single-ended signal, the received voltage includes the signal voltage and a noise voltage component equal to a difference between the (unequal) noise voltages.
Electrical impedances of conductors carrying differential signals, on the other hand, are typically equal as described above. As a result, noise voltages induced in the conductors are substantially equal. With a differential signal, the received voltage includes the signal voltage and a noise voltage component equal to a difference between the (substantially equal) noise voltages. Noise voltage components with differential signals are typically much smaller than those with single-ended signals.
A difference between a maximum level and a minimum level of a signal defines a “dynamic range” of the signal. As voltages on conductors carrying a differential signal are equal and opposite, given a fixed power supply voltage range, the dynamic range of the differential signal may be as much as twice that of a single-ended signal.
Due to the greater dynamic range and the tendency for noise voltages induced in conductors to be equal (and therefore substantially canceling), signal-to-noise ratios with dynamic signals are often much greater than those with single-ended signals.
It is noted the R-C hybrid SAR ADC 10 of FIG. 1 cannot provide the benefits of differential signaling (e.g., common-mode noise cancellation, greater dynamic range, and greater signal-to-noise ratio) due to the many single-ended structures therein (e.g., the resistor string 12 and the capacitor array 14). At the same time, differential amplifiers and cables are often more complex and more expensive to produce than single-ended amplifiers and cables, and differential input signals are often not available. A need thus exists for an analog-to-digital converter (ADC) that can receive either a single-ended analog input voltage or a differential analog input voltage, and uses differential signaling techniques to produce an output signal having a lower noise level than is typical of current ADCs.